Intel’s research team announced on Saturday that the company believes it will help it continue to accelerate and shrink its work on computing chips over the next ten years. Several of these technologies are designed to stack various parts of the chip on top of each other.
Intel’s research component group presented this work in the form of a paper at an international conference in San Francisco. The Silicon Valley company is trying to regain its lead in manufacturing the smallest and fastest chips, but in recent years it has lost out to competitors such as TSMC and Samsung Electronics.
Although Intel CEO Pat Gelsinger has developed a business plan aimed at regaining its leading position by 2025, the research published on Saturday allows us to understand how Intel plans to compete after 2025.
Intel is one of the ways to pack more computing power into the chip by stacking “tiles” or “chiplets” in three dimensions instead of using all the chips as a two-dimensional piece. Intel’s work demonstrated on Saturday can allow the number of connections between stacked tiles to increase 10 times, which means more complex tiles can be stacked on top of each other.
But perhaps the biggest advancement shown on Saturday was a research paper showing a method of stacking transistors-microswitches that form the most basic building blocks of a chip with ones and zeros representing digital logic-superimposed on each other.
Intel believes that this technology will increase the number of transistors that can fit into a given area on the chip by 30% to 50%. Increasing the number of transistors is the main reason why chips have been getting faster for the past 50 years.
“By directly stacking the devices together, we obviously saved area,” Paul Fisher, director of Intel’s component research department and senior principal engineer, told Reuters in an interview. “We are reducing the length of the interconnection and really saving energy, making it not only more cost-effective, but also more performant.”